Area Array Packaging Handbook: Manufacturing and Assembly by Ken Gilleo

By Ken Gilleo

*Covers layout, packaging, development, meeting, and alertness of all 3 techniques to region Array Packaging: Ball Grid Array (BGA), Chip Scale package deal (CSP), and turn Chip (FC) *Details the professionals and cons of every know-how with various functions *Examines packaging ramifications of excessive density interconnects (HDI)

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The simplified connection schemes may not allow area configurations. Some simple CSPs bring the connections to the sides of the package so that no through-the-carrier conductors are needed. The second reason is that low-count packages, such as those for single memory chips, do not always need to use area. This also makes inspection easier because the connections can be examined visually. Area Array. Area array packaging can be as simple as a double row of connector balls around the perimeter of a chip carrier.

Their inefficiencies produce by-product heat. Some ICs can produce considerable heat, around 100 W for powerful new CPUs. The faster clock rates, greater number of transistors per chip, and diminishing size of the chip all come together to create a potential thermal catastrophe. The chip produces heat faster than it can be dissipated, causing the temperature to rise. The hot chip becomes even more inefficient and produces a higher output of heat. This thermal runaway condition finally reaches a level where the chip breaks down and is destroyed.

All three types of first-level chip connections are used with flex, DCA, WB, and TAB. The TABlike connection is the most unusual and does not have an equivalent in rigid systems. IBM was the first to use TAB inner-lead bonding while removing the outer-lead connection. The leads from the chip were routed into an area array pattern and connected to metal bumps by means of vias through the thin polyimide film. This innovation kept the best of TAB and eliminated the troublesome outer leads. What’s more, the package was transformed into SMT.

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